The present invention is generally related to digital line delays. In particular, the present invention is related to a digital line delay based on a read/write memory structure that can be utilized as a video line delay in digital image processing circuitry.
Many digital image processing techniques require that multiple lines of image data be simultaneously available in order to perform various convolution operations such as interpolation, filtering and enhancement. Accordingly, a video line delay device must be utilized to provide delayed image data in order to accomplish the desired image processing. A video line delay device can generally be described as a sequential access device in which current pixel data is input and delayed pixel data is output. Sequential access can be accomplished either by configuring the video line delay as a sequentially addressed read/write memory or by using shift registers to shift pixel data from one register to the next until the pixel data is output after the desired delay time has been reached.
Recent advances in VLSI technology has led to the capability of integrating whole digital signal processing (DSP) systems on a single chip. It would be desirable to apply VLSI technology to integrate the circuitry required to accomplish digital image processing (including a video line delay) into a single chip that could be easily incorporated within the body of electronic still/motion video cameras or other electronic imaging devices. Camera applications, in particular, necessitate low power and space requirements for the digital image processing circuitry. The space criterion, together with the fact that DSP real-time systems are pipelined, dictates the use of dynamic rather than static logic for the video line delay architecture, as in general, more transistors per cell are required for static logic designs. The low power requirement also suggests the use of DRAM architecture rather than dynamic shift-registers, as DRAM architecture only requires that the addressing circuits be switched each cycle, whereas each element or pixel cell would have to be switched in a shift-register architecture.
Another disadvantage of a shift-register video line delay is that variable or programmable delay lengths are not practically feasible, as the output of all the registers would have to be multiplexed to the output of the video line delay. The requirement for a variable or programmable delay length is desirable in order to create a video line delay that can be utilized in cameras operating at different video standards such as National Television standards Committee (NTSC), Phase-Alternation Line (PAL) and International Radio Consultive Committee (CCIR) and with different size image sensors. The CCIR standard requires a line length of 720 pixels with a 13.5 MHz pixel rate. The NTSC and PAL standards can use a lesser or greater number of pixels per line at slower or faster rates. For example, the NTSC standard can use 570 active pixels per line. Thus, it would be desirable to provide a video line delay that could be programmed to operate in conjunction with a variety of video standards.
While the above-described requirements for size, low power consumption and variable delay length would appear to lead to the use of DRAM architecture for video line delays, conventional DRAM architectures are not particularly suited for implementation as video line delays. For example, most memory devices require some form of address decoding and multiplexing of the bit lines to output data as shown in FIG. 1. For a READ operation to occur in the illustrated example, the upper six address bits (a2 to a7) are decoded by a word-line decoder to enable the word lines that evaluate the four memory cells which respectively correspond to the same bit (for example bit 0) of four different words. The lowest two address bits (a0, a1) are decoded to control a 4:1 multiplexer that selects one of the four memory cells. A counter must be used to provide the sequential access. The use of the multiplexer which requires address decoding and a counter adversely effects the amount of power and chip space required for the architecture.
In view of the above, the object of the present invention is to provide a video line delay architecture that requires a minimum of chip space, has low power requirements, is variable or programmable in length, and is flexible to permit changes in aspect ratio. In addition, the present invention is directed toward providing a memory based line delay architecture that is "Self-Multiplexing", i.e., does not require address decoding or external control signals as in conventional memory devices.